A content addressable memory system (hereafter simply a CAM system) is a memory system in which individual memory elements are not exclusively indexed by a unique address. Instead, a memory element in a CAM system may be addressed by a portion of the data within the memory element. The way in which a memory cell in a CAM system is addressed distinguishes a CAM system from a conventional random access memory (RAM) or a read only memory (ROM).
A particular data word stored in a RAM cell or a ROM cell is accessed by supplying a unique address to the memory system associated with the desired memory element. In a CAM memory system, a "tag" is supplied to the memory system. The CAM memory system compares the tag to a subset of the data bits contained in each memory element. Generally, the portion of each memory element that contains this subset of memory bits is referred to as the CAM. Each CAM is associated with a conventional memory element containing other data bits. The CAM (or CAMs) that contains data bits logically equivalent to the input tag "matches" and asserts a logic signal referred to as a "matchline." The asserted matchline causes the CAM memory system to output the other data bits associated with the matching CAM. The other data bits are the desired data word. The number of matches depends upon the particular implementation of the CAM and its operation history. The number of matches may range from zero to the number of memory elements within the CAM memory system.
CAM memory systems are often used as high speed memory caches in data processing applications. In a data processing application, each CAM contains data corresponding to a unique address of the other data bits associated with the CAM. During operation, the data processing system periodically requests data associated with a unique address. The data processing system first compares the unique address to the contents of each CAM. If any CAM matches the unique address, then the CAM memory system forwards the data associated with the matching CAM to the data processing system. If no CAM matches the input tag, then the data processing system forwards the unique address to a conventional, slower RAM system.
The operation of CAM systems is known in the art. Generally, during a first phase of a clock signal each of a set of matchline nodes is precharged to a voltage level corresponding to a high logic level. During a second phase of the clock signal, a tag is input to each CAM and a comparison made between each bit of the tag and a corresponding bit within the CAM. Each bit within a CAM may discharge the matchline node corresponding to the memory element if the bit does not match the corresponding tag bit. If all tag bits match the corresponding bits within a particular CAM, then no bit discharges the matchline node. According to conventional nomenclature, a high matchline node is an asserted matchline. The asserted matchline causes the data word associated with the matching CAM to be output from the CAM memory system.
Known CAM memory systems have at least one disadvantage when incorporated into high performance systems. Known CAM memory systems only allow a portion of one-half of a clock cycle for the match line note to drive the output of the associated memory element. Current and foreseeable high performance systems are designed to operate at clock speeds at or very near the physical limitations imposed by the system's manufacturing processes. Therefore, a portion of one-half of one clock cycle may be less than the minimum time required to evaluate an output data word.